1. Field of the Invention
The present invention relates to a semiconductor device and to a method for fabricating the semiconductor device, and, in particular, to a MISFET transistor which is provided with highly reliable insulating films and to a method for fabricating the MISFET transistor.
2. Description of Background
Recently, large scale integrated circuits (LSIs) have been utilized in the important parts of computers and communication equipment. Therefore, to improve the performance of the LSI units, each of the metal-insulator-semiconductor field effect transistors (MISFETs) which are fundamental LSI devices has been miniaturized.
However, the miniaturization of the device has caused several types of drawbacks according to the so-called scaling rule, so that the reliability of the device has deteriorated.
For example, the miniaturization of the device in the MISFETs results in the gate insulating films becoming thin so that a so-called time dependent dielectric breakdown (TDDB) phenomenon is generated. Therefore, the insulation reliability of the gate films deteriorates in cases where the device is utilized for a long time.
Moreover, in cases where the gate electrodes are made from polycrystalline silicon in a first conventional MISFET transistor, impure atoms existing in the gate electrodes penetrate through the thinned gate insulating films so that the impure atoms are diffused over the surface area of a substrate in several processes including thermal oxidation treatment performed after the fabrication of gate electrodes. As a result, the impurity concentration in a channel region fabricated in the surface area of the substrate is shifted, so that control of the threshold voltage of the device becomes difficult. Therefore, malfunctions are easily caused and the operational reliability of the device deteriorates in a conventional MISFET transistor.
Therefore, to solve drawbacks caused in the gate insulating films, nitrogen atoms are added to the gate insulating film in the conventional MISFET transistor.
FIGS. 1A, 1B, and 1C are respectively cross sectional views of a second conventional MISFET transistor, showing the fabricating processes for adding the nitrogen atoms to the gate insulating films in the transistor.
As shown in FIG. 1A, a thin thermally oxidized film 14 is initially produced by a thermal oxidation method on a P-type silicon substrate 11 in which an N well region 12 and field oxide films 13 are produced. Thereafter, for example, a first ramp heating process is performed for 60 seconds at a temperature of 1150.degree. C. in a gas atmosphere which includes ammonia NH.sub.3, then a second ramp heating process is performed for 60 seconds at a temperature of 1150.degree. C. in a dry oxygen atmosphere, so that nitrogen atoms are added to the thin thermally oxidized film 14. Thereafter, a polycrystalline silicon film 15 is deposited over the entire silicon substrate 11, and high doses of BF.sub.2 ions are then implanted into the polycrystalline silicon film 15 so that P type silicon film 16 is produced.
Thereafter, as shown in FIG. 1B, a resist pattern is drawn on the P type silicon film 16 by a photolithography method, and the P type silicon film 16 and the thin thermally oxidized film 14 are then etched while parts of the P type silicon film 16 on which the resist pattern is drawn are masked, so that a gate insulating film 17 formed by the remaining thermally oxidized film 14 and a gate electrode 18 formed by the remaining P type silicon film 16 are produced. Thereafter, boron ions are implanted into the silicon substrate 11 while utilizing the gate electrode 18 as a mask for preventing the boron ions from being implanted into the gate insulating film 17, so that a source field 19 and a drain field 20 are produced in self-alignment with the insulating film 17.
Finally, as shown in FIG. 1C, a layer insulating film 21 is fabricated over the entire silicon substrate 11, then parts of the layer insulating film 21 are opened to produce contact holes through which the source field 19 and the drain field 20 are respectively exposed. Thereafter, wire fields 22 are deposited, and a passivation film 23 is then deposited over the entire silicon substrate 11, so that a device formed by a gate region 17, 18, the source region 19, the drain region 20 and the like is fabricated. Therefore, a second conventional MISFET transistor 24 formed by many devices is fabricated.
In the MISFET transistor 24 fabricated by the above mentioned processes, a thin film 25 with added nitrogen atoms is produced in an interface of the N well region 12 adjacent to the gate insulating film 17 because the nitrogen atoms added to the gate insulating film 17 are diffused in the N well region 12. Therefore, the thin film produced in the interface 25 prevents the boron atoms implanted in the gate electrode 18 from diffusing into the N well region 12 through the gate insulating film 17. As a result, the performance in controlling the threshold voltage can be improved in the MISFET transistor 24, so that the operational reliability of the devices in the MISFET transistor 24 is improved. Moreover, because the number of defects in the gate insulating film 17 is decreased, the TDDB characteristics are improved so that the operational reliability of the gate insulating film 17 is ensured.
However, when the thin thermally oxidized film 14 is produced by the thermal oxidation method and when the nitrogen atoms are added to the thin thermally oxidized film 14, stress is generated on the surface of the silicon substrate 11, so that tensile stress is produced in the silicon substrate 11. Therefore, when the effective gate length (the channel length) is short, there is a new drawback in that the threshold voltage is shifted so that the operational reliability of the MIS transistor 23 deteriorates.
FIG. 2 is a graphic view of experimental results showing the shift of the threshold voltage.
An abscissa indicates the effective gate length L.sub.eff and an ordinate indicates the threshold voltage V.sub.th. Moreover, a curve A connecting the white circles indicates experimental results obtained when the tensile stress caused in the silicon substrate 11 is comparatively small. On the other hand, a curve B connecting the black triangles indicates experimental results obtained when the tensile stress caused in the silicon substrate 11 is comparatively large.
As shown in FIG. 2, in cases where the tensile stress caused in the silicon substrate 11 is comparatively small, the threshold voltage is not shifted even if the effective gate length is shortened to about 2 .mu.m. On the other hand, in cases where the tensile stress caused in the silicon substrate 11 is comparatively large, the threshold voltage is distinctly shifted even if the effective gate length is very large.
To improve the performance of each device, the improvement of the electronic performance of the conventional MISFET transistor is described.
FIG. 3 is a cross sectional view of a third conventional MISFET transistor.
As shown in FIG. 3, in the third conventional MISFET transistor, a silicon oxide film 27 is, for example, produced by the thermal oxidation method in the same manner as the gate insulating film 17 in the second conventional MISFET transistor. Thereafter, a silicon nitride film 26 is deposited on the silicon oxide film 27 by a liquid phase chemical vapor deposition (LPCVD) method, so that a lamination layer consisting of the silicon oxide and silicon nitride films 26, 27 is formed as a gate insulating film 28.
In the above configuration of the third conventional MIS transistor, because the silicon nitride film 26 is deposited in exchange for the upper part of the silicon oxide 17, the permittivity of the gate insulating film 28 is higher than that of the gate insulating film 17 formed by only the silicon oxide film. Therefore, the capacitance of the gate insulating film 28 formed by the laminated layers is increased so that load drivability (that is, drain current Id) of the third conventional MISFET transistor is improved.
However, the third conventional MISFET transistor with the laminated gate insulating film 28 has a drawback in that device characteristics such as the threshold value and charge-pumping current are easily shifted by the hot-carrier phenomenon.
To describe the above drawback in detail, many experimental results relating to the shift of the threshold value and the charge-pumping current were obtained as follows.
FIG. 4 shows, in tabular form, sample fabrication conditions for the nitrified silicon oxide films 26 and the pure silicon oxide films 27 with various thicknesses in the third conventional MISFET transistor.
As shown in FIG. 4, various combinations of nitride and oxide thicknesses were chosen for the experiments. A symbol "PO" represents the first conventional MISFET transistor which is provided with only a pure silicon oxide film as the gate insulating film. The experimental results of the first conventional MISFET transistor are shown for reference. On the other hand, a symbol "ON" represents the third conventional MISFET transistor which is provided with laminated gate insulating film 28 formed by the silicon nitride oxide film 26 and the pure silicon oxide film 27.
the experimental results are designated by the symbols "ON xs and "PO". For example, "ON 5-6n" represents the third conventional MISFET transistor provided with the pure silicon oxide film 27 (5 nm in thickness) and the silicon nitride film 26 (6 nm in thickness).
FIG. 5 shows the dependence of a drain current I.sub.DO at a drain voltage V.sub.D =3 V and an effective gate voltage V.sub.G -V.sub.TH =3 V on the physical thickness of the gate insulating film 28 for the various types of films.
In FIG. 5, the X-axis indicates the physical thickness of the gate insulating film 28. The Y-axis indicates the drain current I.sub.DO designating the load drivability.
As shown in FIG. 5, the third conventional MISFET transistor has excellent drivability compared with those of the first conventional MISFET transistors with the pure silicon oxide film. The reason is that the nitrified silicon oxide film has high permittivity.
FIGS. 6A and 6B show the initial threshold voltage of the n-channel and p-channel MISFET transistors before the hot carrier stress is applied to the MISFET transistors, the transistors being provided with the various gate films 26, 27 shown in FIG. 4.
In FIGS. 6A and 6B, the X-axis indicates an oxide equivalent thickness Tox of the laminated gate film 28. The oxide equivalent thickness is calculated by converting the thickness of the silicon nitride film 26 into the equivalent thickness of the silicon oxide film without changing the capacitance. The Y-axis indicates the threshold voltage V.sub.th.
As shown in FIGS. 6A and 6B, the absolute values of the threshold voltage V.sub.th increase with an increase of the film thickness of the silicon nitride film 26.
FIGS. 7A and 7B show the initial charge-pumping current of the n-channel and p-channel MISFET transistors before hot carrier stress is applied to the transistors, the transistors being provided with the various gate films 26, 27 shown in FIG. 4.
In FIGS. 7A and 7B, the X-axis indicates the oxide equivalent thickness Tox of the laminated gate insulating film 28. The Y-axis indicates the initial charge-pumping current I.sub.CP.
As shown in FIGS. 7A and 7B, the absolute values of the initial charge-pumping currents I.sub.CP increase with the increase of the film thickness of the nitrified silicon oxide film 26.
FIGS. 8A and 8B are graphic view of experimental results respectively showing the shift of the threshold voltage caused by the hot carrier stress applied to the third conventional MISFET transistor for 1000 seconds, the transistor being provided with the laminated gate insulating film 28 shown in FIG. 4.
The experimental result shown in FIG. 8A were obtained in an N channel MIS transistor provided with a gate insulating film formed with a channel length of 1 .mu.m and a channel width of 10 .mu.m. Each experimental result shown in FIG. 8B is obtained in an P channel MIS transistor provided with a gate film formed by a channel length 1 .mu.m and a channel width 10 .mu.m.
To cause hot carrier stress in the substrate, a drain voltage of 5 V were applied to the N channel MIS transistor (a drain voltage of -5 V for the P channel MIS transistor) and a specific voltage was applied to a gate electrode for 1000 seconds so as to generate the maximum substrate current. The substrate current was generated by a prescribed voltage applied to the gate electrode so as to discharge the electric charges trapped in the gate insulating film to the substrate.
In FIGS. 8A and 8B, the X-axis is the oxide equivalent thickness Tox of the laminated gate insulating film 28. The Y-axis is the threshold voltage shift .DELTA.V.sub.th which was obtained by subtracting a threshold voltage value measured before the hot carrier stress was applied to the substrate from another threshold voltage value measured after the hot carrier stress was applied to the substrate.
As shown in FIGS. 8A and 8B, the threshold voltage shift is extremely large in the case of 6 nm nitride samples "ON 3-6n" and "ON 5-6n". The reason is that electrons can be easily trapped in the silicon nitride film 26. This means that the silicon nitride film 26 needs to be equal to or less than 4 nm in thickness, and as small as 3 nm if possible.
FIGS. 9A and 9B are graphic views of the experimental results showing the shift of the charge-pumping current caused by the hot carrier stress applied to the third conventional MIS transistors for 1000 second, the transistors being provided with the laminated gate insulating film 28 shown in FIG. 4.
The experimental results shown in FIG. 9A were obtained by an N channel MIS transistor provided with a gate insulating film formed with a channel length of 1 .mu.m and a channel width of 10 .mu.m. The experimental results shown in FIG. 9B were obtained by an P channel MIS transistor provided with a gate insulating film formed with a channel length of 1 .mu.m and a channel width of 10 .mu.m.
To cause hot carrier stress in the substrate, a drain voltage of 5 V was applied to the N channel MIS transistor (a drain voltage of -5 V for the P channel MIS transistor) and a specific voltage was applied to a gate electrode for 1000 seconds, so as to generate the maximum substrate current.
In FIGS. 9A and 9B, the X-axis is an oxide equivalent thickness Tox of the laminated gate insulating film 28 in the same manner as in FIGS. 8A and 8B. The Y-axis is a charge-pumping current shift .DELTA.Icp which was obtained by subtracting a charge-pumping current measured before the hot carrier stress was applied to the substrate from another charge-pumping current measured after the hot carrier stress was applied to the substrate. The charge-pumping current shift .DELTA.Icp designates the number of generated hot carriers or the density of interface-states resulting from the hot carriers because the charge-pumping current is proportional to the density of the interface-states.
As shown in FIG. 9A, the dependence of the charge-pumping current shift .DELTA.I.sub.CP on the film thickness of the silicon nitride film 26 is weak in the n-channel MISFET transistors. On the other hand, as shown in FIG. 9B, the dependence of the charge-pumping currents shift .DELTA.I.sub.CP on the film thickness of the silicon nitride film 26 is strong in the p-channel MISFET transistors. The reason is that a large number of interface states are generated when the film thickness of the silicon nitride film 26 is small, particularly in the 3 nm case.
Accordingly, to withstand the hot carrier stress, the MISFET transistor must be formed by the laminated gate insulating film in which the film thickness of the silicon nitride is more than 3 nm.
Moreover, as shown in FIGS. 8D and 8B, it is difficult to reduce both the threshold voltage shift .DELTA.V.sub.th and the charge-pumping current shift .DELTA.Icp at any film thickness in the MISFET transistor.
Accordingly, there is a drawback that the operational reliability of the MIS transistor with the laminated gate insulating film deteriorates regardless of whether the P channel MIS transistor is provided with a thin or thick silicon nitride film.
Conventionally, a MOSFET transistor comprises:
a substrate; PA1 a source region produced in the substrate; PA1 a gate region produced in the substrate adjacent to the source region; PA1 a drain region, produced in the substrate adjacent to the gate region, for receiving charges provided from the source region, PA1 a gate oxidation film produced on the gate region; PA1 a gate electrode produced on the gate oxidation film; PA1 a source electrode; and PA1 a drain electrode. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate; PA1 a silicon nitride film producing step for producing a thin silicon nitride film on the silicon oxide film; PA1 a thermal nitridation step for thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas; PA1 a conductive film producing step for producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas; PA1 a gate region producing step for producing a gate region from the silicon oxide film produced in the silicon oxide film producing step, the silicon nitride film nitrided in the thermal nitridation step, and the conductive film produced in the conductive film producing step, a channel region being positioned under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and the gate region, the semiconductor device being fabricated by the gate region, the channel region, the source region, the drain region, and the wiring regions. PA1 a source region which is produced in one upper region of the silicon substrate; PA1 a drain region for receiving a drain current from the source region through a channel region, the drain region being produced in another upper region of the silicon substrate; PA1 a silicon oxide film for insulating gate charge from the channel region of the silicon substrate, the film being positioned on the channel region; PA1 a thin silicon nitride film positioned on the silicon oxide film for insulating the gate charge from the channel region of the silicon substrate, the number of interface states in the thin silicon nitride film being reduced by a rapid thermal nitridation in an atmosphere of nitrogenous gas; PA1 a gate electrode for accumulating the gate charge, the gate electrode being positioned on the thin silicon nitride film; and PA1 wiring regions for applying the gate charge to the gate electrode and the drain current to the source region and receiving the drain current from the drain region. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate; PA1 a silicon nitride film producing step for producing a thin silicon nitride film on the silicon oxide film; PA1 a thermal nitridation step for thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas; PA1 a silicon nitride film oxidizing step for oxidizing the silicon nitride film nitrided in the thermal nitridation step; PA1 a conductive film producing step for producing a conductive film on the silicon nitride film oxidized by the dry oxygen; PA1 a gate region producing step for producing a gate region from the silicon oxide film produced in the silicon oxide film producing step, the silicon nitride film oxidized in the silicon nitride film oxidizing step, and the conductive film produced in the conductive film producing step, a channel region being positioned under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and gate region, the semiconductor device being fabricated by the gate region, the channel region, the source region, the drain region, and the wiring regions. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate; PA1 a silicon nitride film producing step for producing a thin silicon nitride film on the silicon oxide film; PA1 a thermal annealing step for annealing the silicon nitride film in an atmosphere of argon gas; PA1 a conductive film producing step for producing a conductive film on the silicon nitride film annealed in the atmosphere of argon gas; PA1 a gate region producing step for producing a gate region from the silicon oxide film produced in the silicon oxide film producing step, the silicon nitride film annealed in the thermal annealing step, and the conductive film produced in the conductive film producing step, a channel region being positioned under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and the gate region, the semiconductor device being fabricated by the gate region, the channel region, the source region, the drain region, and the wiring regions. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate; PA1 a silicon nitride film producing step for producing a thin silicon nitride film on the silicon oxide film; PA1 a rapid thermal annealing step for anealing the silicon nitride film in an atmosphere of argon gas at temperatures ranging from 700.degree. C. to 1200.degree. C. for a short time; PA1 a silicon nitride film oxidizing step for oxidizing the surface of the annealed silicon nitride film by dry oxygen in a furnace atmosphere at a temperature of 800.degree. C. for 30 minutes; PA1 a conductive film producing step for producing a conductive film on the silicon nitride film oxidized by the dry oxygen; PA1 an etching step for etching the silicon oxide and nitride films and the conductive film to a prescribed pattern so as to produce a gate region formed by the remaining silicon oxide and nitride films and the remaining conductive film, a channel region being positioned under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and the gate region. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate by a liquid phase deposition method; PA1 a silicon oxide film densifying step for densifying the silicon oxide film by vaporizing water included in the silicon oxide film; PA1 a thermal nitridation step for thermally nitriding the silicon oxide film densified in the silicon oxide film densifying step; PA1 a nitrided silicon film re-oxidizing step for re-oxidizing the surface of the nitrided silicon oxide film in an atmosphere of dry oxygen at temperatures around 1100.degree. C. for a short time; PA1 a conductive film producing step for producing a conductive film on the re-oxidized silicon nitride film; PA1 a gate region producing step for producing a gate region from both the silicon oxide film produced in the silicon oxide film producing step and the conductive film produced in the conductive film producing step, a channel region being positioned under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and the gate region, the semiconductor device being fabricated by the gate region, the channel region, the source region, the drain region, and the wiring regions. PA1 a silicon oxide film producing step for producing a silicon oxide film on the silicon substrate; PA1 a rapid thermal nitridation step for thermally nitriding the silicon oxide film in an atmosphere of nitrogenous gas by a rapid thermal nitridation method so as to produce an interface region in which the nitrogen concentration is between 0.2 atom % and 1.0 atom %, the interface region being positioned between the silicon oxide film and the silicon substrate; PA1 a conductive film producing step for producing a conductive film on the silicon oxide film; PA1 a gate region producing step for producing a gate region from both the silicon oxide film nitrided in the rapid thermal nitridation step and the conductive film produced in the conductive film producing step, a channel region being formed under the gate region in the silicon substrate; PA1 a source region producing step for producing a source region in the silicon substrate adjacent to one side of the channel region; PA1 a drain region producing step for producing a drain region in the silicon substrate adjacent to another side of the channel region; and PA1 a wiring region producing step for producing wiring regions on the source region, the drain region, and the gate region, the semiconductor device being fabricated by the gate region, the channel region, the source region, the drain region, and the wiring regions. PA1 a source region which is produced in one upper region of the silicon substrate; PA1 a drain region for receiving a drain current from the source region through a channel region, the drain region being produced in another upper region of the silicon substrate; PA1 a silicon oxide film positioned on the channel region for insulating gate charge from the channel region of the silicon substrate, the film being nitrided by a rapid thermal nitridation method in an atmosphere of nitrogenous gas; PA1 an interface region in which the nitrogen concentration is between 0.2 atomic % and 1.0 atom %, the interface region being formed between the silicon oxide film and the silicon substrate; PA1 a gate electrode for accumulating the gate charge, the gate electrode being positioned on the silicon oxide film; and PA1 wiring regions for applying the gate charge to the gate electrode and the drain current to the source region and receiving the drain current from the drain region.
In the above configuration of the MOSFET transistor, to prevent impure atoms existing in the gate electrode from diffusing to the substrate and to improve the operational reliability of the MOS transistor, the nitrogen concentration of the gate oxidation film is set from 2% to 10%. In other words, the nitrogen concentration of the gate oxidation film is very high.
However, because the nitride is highly concentrated in the gate oxidation film, a great deal of Coulomb scattering is generated by fixed charges existing in the gate oxidation film. Therefore, the transconductance Gm deteriorates in the conventional P channel and N channel MOSFET transistors.
Moreover, because the nitride is highly concentrated in the gate oxidation film, the tensile stress is caused in the P type substrate. Therefore, the drivability (drain current) deteriorates in the conventional P channel MOSFET transistor.